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CS5396 CS5397
120 dB, 96 kHz Audio A/D Converter
Features
l 24-Bit
General Description
The CS5396 and CS5397 are complete analog-to-digital converters for stereo digital audio systems. They perform sampling, analog-to-digital conversion and antialias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 100 kHz per channel. The CS5396/97 use a patented 7th-order, tri-level deltasigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The ADCs use a differential architecture which provides excellent noise rejection. The CS5396 has a linear phase filter optimized for audio applications with 0.005 dB passband ripple and >117 dB stopband rejection. The CS5397 has a nonaliasing filter response with 0.005 passband ripple and >117 dB stopband attenuation. Other features available in both the CS5396 and CS5397 are an optional low group delay filter and a unique psychoacoustic noise shaping filter which subjectively truncates the output to 16, 18 or 20 bits while 24-bit sound quality is preserved. The CS5396/97 are targeted for the highest performance professional audio systems requiring wide dynamic range, negligible distortion and low noise. ORDERING INFORMATION CS5396-KS -10 to 50 C CS5397-KS -10 to 50 C CDB5396/97
VCOM MCLKA ADCTL DACTL CAL SCLK LRCK SDATA1 SDATA2 MCLKD
Conversion l 120 dB Dynamic Range (A-Weighted) l Low Noise and Distortion >105 dB THD + N l Complete CMOS Stereo A/D System Delta-Sigma A/D Converters Digital Anti-Alias Filtering S/H Circuitry and Voltage Reference l CS5396 - digital filter optimized for audio l CS5397 - non-aliasing digital filter l Adjustable System Sampling Rates including 32, 44.1, 48 & 96 kHz l Differential Analog Architecture l Linear Phase Digital Anti-Alias Filtering l 10 Tap Programmable Psychoacoustic Noise Shaping Filter l Single +5 V Power Supply
28-pin SOIC 28-pin SOIC Evaluation Board
VREF
Voltage Reference
Serial Output Interface
Serial Control Port
CS CDIN CCLK
AINLAINL+ S/H
+ -
LP Filter
+ -
DAC AINRAINR+ S/H DAC
Comparator
Digital Decimation Filter (with Low Group Delay Options) Digital Decimation Filter (with Low Group Delay Options) Calibration Microcontroller
Psychoacoustic Filter
+ -
LP Filter
+ -
Comparator
Calibration SRAM
VA
AGND1
AGND2 AGND0 VL LGND
TST0
TST1
VD
DGND
Preliminary Product Information
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1997 (All Rights Reserved)
SEP `97 DS229PP2 1
CS5396 CS5397
TABLE OF CONTENTS
TABLE OF CONTENTS.......................................................................................................2 ANALOG CHARACTERISTICS ..........................................................................................4 DIGITAL FILTER CHARACTERISTICS ..............................................................................5 POWER AND THERMAL CHARACTERISTICS .................................................................6 DIGITAL CHARACTERISTICS............................................................................................6 ABSOLUTE MAXIMUM RATINGS......................................................................................6 RECOMMENDED OPERATING CONDITIONS ..................................................................7 SWITCHING CHARACTERISTICS .....................................................................................7 SPI CONTROL PORT SWITCHING CHARACTERISTICS.................................................9 I2C CONTROL PORT SWITCHING CHARACTERISTICS ...............................................10 GENERAL DESCRIPTION ...............................................................................................12 Stand-Alone vs. Control Port Mode ........................................................................12 STAND-ALONE MODE ....................................................................................................12 Master Clock - Stand-Alone Mode ..........................................................................12 Serial Data Interface - Stand-Alone Mode ..............................................................12 Serial Data- Stand-Alone Mode .......................................................................13 Serial Clock - Stand-Alone Mode ....................................................................13 Left/Right Clock - Stand-Alone Mode ..............................................................13 Master Mode - Stand-Alone Mode ..........................................................................13 Slave Mode - Stand-Alone Mode ............................................................................13 High Pass Filter - Stand-Alone Mode .....................................................................13 Power-up and Calibration - Stand-Alone Mode ......................................................13 Synchronization of Multiple Devices - Stand Alone Mode ......................................14 CONTROL PORT MODE ..................................................................................................14 Access to Control Port Mode ..................................................................................14 Internal Power-On Reset .................................................................................14 Master Clock - Control Port Mode ..........................................................................15 64x vs. 128x Oversampling Modes ........................................................................15 Serial Data Interface - Control Port Mode ..............................................................15 Serial Data - Control Port Mode ......................................................................15 Serial Clock - Control Port Mode .....................................................................15 Left/Right Clock -Control Port Mode ................................................................15 Master Mode- Control Port Mode ...........................................................................17 Slave Mode - Control Port Mode ............................................................................17 Synchronization of Multiple Devices - Control Port Mode ......................................17 Power-up and Calibration - Control Port Mode .......................................................17 High Pass Filter -Control Port Mode .......................................................................17 Input Level Monitoring - Control Port Mode ............................................................18 High Resolution Mode .....................................................................................18 Bar Graph Mode ..............................................................................................18 Dual Digital Audio Outputs .....................................................................................18 Psychoacoustic Filter ..............................................................................................19 Low Group Delay Filter ...........................................................................................19 C Interface Formats ..............................................................................................19 SPI Mode .........................................................................................................19 I2C Mode .........................................................................................................19 Establishing the Chip Address in I2C Mode ....................................................19 ANALOG CONNECTIONS - ALL MODES .......................................................................19 GROUNDING AND POWER SUPPLY DECOUPLING - ALL MODES ............................20 DIGITAL FILTER PLOTS .................................................................................................21 REGISTER DESCRIPTION ...............................................................................................25 PIN DESCRIPTIONS .........................................................................................................31 Power Supply Connections .....................................................................................31 Analog Inputs...........................................................................................................31 Analog Outputs........................................................................................................32 Digital Inputs............................................................................................................32
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Digital Input Pin Definitions for Stand-Alone MODE ............................................... 32 Digital Pin Definitions for CONTROL-PORT MODE................................................ 33 Digital Outputs......................................................................................................... 33 Digital Inputs or Outputs.......................................................................................... 34 Miscellaneous ......................................................................................................... 34 PARAMETER DEFINITIONS............................................................................................. 35 ADDITIONAL INFORMATION........................................................................................... 36 PACKAGE DIMENSIONS ................................................................................................. 37
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ANALOG CHARACTERISTICS (TA = 25C; VA, VL,VD = 5V; Full-scale Input Sinewave, 997 Hz;
Analog connections as shown in Figure 1; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; Logic 0 = 0V, Logic 1 = VD; Parameter Symbol Dynamic Performance Dynamic Range MCLK equal to 24.576 MHz Fs = 48 kHz in 128x Oversampling Mode (A-weighted) Fs = 48 kHz in 128x mode Fs = 96 kHz in 64x mode (A-weighted) Fs = 96 kHz in 64x mode (40 kHz Bandwidth) MCLK equal to 12.288 MHz Fs = 48 kHz in 64x mode (A-weighted) Fs = 48 kHz in 64x mode Total Harmonic Distortion + Noise THD+N Fs = 48 kHz in 128x mode -1 dB (Note 1) -20 dB (Note 1) -60 dB (Note 1) Fs = 96 kHz in 64x mode -1 dB (Note 1) (40 kHz bandwidth) -20 dB (Note 1) -60 dB (Note 1) Fs = 48 kHz in 64x mode -1 dB (Note 1) -20 dB (Note 1) -60 dB (Note 1) Total Harmonic Distortion -1 dB (Note 1) THD Interchannel Phase Deviation Interchannel Isolation Dynamic Range Performance Drift (following calibration) dc Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Offset Error (With high pass filter enabled) Analog Input VIN Full-scale Differential Input Voltage (Note 2) ZIN Input Impedance Differential Common-mode Common-Mode Rejection Ratio CMRR Notes: 1. Referenced to typical full-scale differential input voltage (4.0 Vpp). 2. Specified for a fully differential input {(AINR+)-(AINR-)}.The ADC accepts input voltages up to the analog supplies (VA and AGND). Full-scale outputs will be produced for differential inputs beyond VIN. * Refer to Parameter Definitions at the end of this data sheet. Specifications are subject to change without notice. Min TBD TBD TBD TBD TBD TBD Typ Max Units
120 117 120 114 117 114 105 97 57 105 97 57 105 97 57 0.00056 0.0001 120 0.05 0.05 5 100 0 4 4.5 TBD 82
TBD TBD -
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB % deg dB dB/C dB % ppm/C LSB Vpp k k dB
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD -
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DIGITAL FILTER CHARACTERISTICS
Parameter (TA = 25 C; VA, VL,VD = 5V5%; Fs = 48 kHz) CS5396 Symbol Min 0 0.5542 117 tgd tgd 0 0 0.646 0.323 86 tgd tgd (Note 3) (Note 3) (Note 3) 34/Fs 34/Fs 10/Fs 1.8 20 5.3 0.0 0 0.0 0.375 0.188 0.015 0 0 34/Fs 34/Fs 10/Fs 1.8 20 5.3 0.0 0 0.0 0.375 0.188 0.015 127.35 63.68 Typ Max 0.4604 0.005 Min 0 117 CS5397 Typ Max 0.3958 0.005 63.50 Unit Fs dB Fs dB s s s Fs Fs dB Fs Fs dB s s Hz Hz Deg dB
High-Performance Filter Passband(-0.01 dB) Passband Ripple Stopband Stopband Attenuation Group Delay (Fs = Output Sample Rate) 128x Oversampling Mode 64x Oversampling Mode
Group Delay Variation vs. Frequency
63.45 0.4979
Low Group Delay Filter Passband(-0.01 dB) 128x Oversampling Mode 64x Oversampling Mode Passband Ripple Stopband 128x Oversampling Mode 64x Oversampling Mode Stopband Attenuation
Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency
127.35 0.646 63.68 0.323 86 -
High Pass Filter Characteristics Frequency Response-3.0 dB -0.036 dB Phase Deviation@ 20Hz Passband Ripple
Notes: 3. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
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POWER AND THERMAL CHARACTERISTICS
(TA = 25 C; VA, VL,VD = 5V5%; Fs = 48 kHz; Master Mode) 64X oversampling MCLK=12.288 MHz Parameter Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) Power Consumption(Normal Operation) (Power-Down Mode) Power Supply Rejection Ratio (1 kHz) Allowable Junction Temperature Junction to Ambient Thermal Impedance TJA PSRR VA+VL VD VA+VL VD Symbol IA ID IA ID Min Typ 150 65 2 2 1075 20 65 45 Max TBD TBD TBD 135 128X oversampling MCLK=24.576 MHz Min Typ 160 125 3 3.5 1425 33 65 45 Max TBD TBD TBD 135 Unit mA mA mA mA mW mW dB C C/W
DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = -20 A Low-Level Output Voltage at Io = 20 A Input Leakage Current
(TA = 25 C; VA, VL,VD = 5V5%) Symbol VIH VIL VOH VOL Iin Min 2.4 VD - 1.0 Typ Max 0.8 0.4 10 Units V V V V A
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, All voltages with respect to ground.)
Parameter DC Power Supplies: Analog Logic Digital |VA - VD| (Note 6) |VA - VL| (Note 6) |VD - VL| (Note 6) (Note 4) (Note 5) (Note 5) Symbol VA VL VD Min -0.3 -0.3 -0.3 Typ Max +6.0 +6.0 +6.0 0.4 0.4 0.4 Units V V V V V V
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Iin VIN VIND TA Tstg
AGND-0.7 -0.3 -55 -65
-
10 VA+0.7 VD+0.7 +50 +150
mA V V C C
Notes: 4. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 5. The maximum over/under voltage is limited by the input current. 6. Applies to normal operation. Greater differences during power up/down will not cause SCR latch-up. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 6 DS229PP2
CS5396 CS5397
RECOMMENDED OPERATING CONDITIONS
to ground.) Parameter Positive Digital Positive Logic Positive Analog |VA - VD| (Note 6) Ambient Operating Temperature (Power Applied) DC Power Supplies: Symbol VD VL VA Min 4.75 4.75 4.75 -10 Typ 5.0 5.0 5.0 Max 5.25 5.25 5.25 0.4 +50 Units V V V V C (AGND, DGND = 0V, all voltages with respect
TA
Specifications are subject to change without notice.
SWITCHING CHARACTERISTICS (TA = 25 C; VA = 5V5%; Inputs: Logic 0 = 0V,
Logic 1 = VA = VD; CL = 20 pF) Parameter Output Sample Rate MCLK Period MCLK Low MCLK High MCLK Fall Time Master Mode SCLK falling to LRCK SCLK falling to SDATA valid SCLK duty cycle Slave Mode LRCK Period LRCK duty cycle SCLK Period SCLK Pulse Width Low SCLK Pulse Width High SCLK falling to SDATA valid LRCK edge to MSB valid SCLK rising to LRCK edge delay LRCK edge to rising SCLK setup time Symbol Fs tclkw tclkl tclkh tclkft tmslr tsdo Min 2 39.06 26 26 -20 10 4 x tclw 2 x tclw 60 tclw + 20 ns tclw + 20 ns Typ 50 50 Max 100 1950 8 +20 20 500 tclw + 20 ns tclw + 20 ns Units kHz ns ns ns ns ns ns % s % ns ns ns ns ns ns ns
1/Fs tsclkw tsclkl tclkh tdss tlrdss tslr1 tslr2
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t slr1 t slr2
t sclkh t sclkl
SCLK output t mslr LRCK output t sdo SDATA MSB MSB-1
SCLK input t sclkw LRCK input t lrdss SDATA MSB MSB-1 t dss MSB-2
SCLK to SDATA & LRCK - MASTER mode Serial Data Format, Left Justified
SCLK to LRCK & SDATA - SLAVE mode Serial Data Format, Left Justified
t slr1 t slr2
SCLK output t mslr LRCK output t sdo SDATA MSB
t sclkh t sclkl
SCLK input t sclkw LRCK input t dss SDATA MSB MSB-1
SCLK to SDATA & LRCK - MASTER mode Serial Data Format, I2S compatible
SCLK to LRCK & SDATA - SLAVE mode Serial Data Format, I2S compatible
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SPI CONTROL PORT SWITCHING CHARACTERISTICS
Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 20 pF) Parameter Symbol fsck tcsh tcss tscl tsch tdsu (Note 7) (Note 8) (Note 8) tdh tr2 tf2 Min 1.0 20 66 66 40 15 Max 6 100 100 Unit MHz s ns ns ns ns ns ns ns (TA = 25 C; VD, VA = 5V 5%;
SPI Mode
CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN
Notes: 7. Data must be held for sufficient time to bridge the transition time of CCLK. 8. For FSCK < 1 MHz.
CS
t css CCLK t r2 CDIN
t scl
t sch
t csh
t f2
t dsu t dh
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I2C CONTROL PORT SWITCHING CHARACTERISTICS
Inputs: Logic 0 = DGND, Logic 1 = VD; CL = 20 pF) Parameter Symbol Min 4.7 4.0 4.7 4.0 4.7 0 250 4.7 Max 100 1 300 Unit kHz s s s s s s ns s ns s (TA = 25 C; VD, VA = 5V 5%;
I2C(R)
Mode
(Note 9)
fscl tbuf thdst tlow thigh tsust (Note 10) thdd tsud tr tf tsusp
CCLK Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition CDIN Hold Time from CCLK Falling CDIN Setup Time to CCLK Rising Rise Time of Both CDIN and CCLK Lines Fall Time of Both CDIN and CCLK Lines Setup Time for Stop Condition
Notes: 9. Use of the I2C(R) bus interface requires a license from Philips. 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop
CDIN t buf
Start
Repeated Start
Stop
t hdst
t high
t
hdst
tf
t susp
CCLK t t t sud t sust tr
low
hdd
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+5V Analog
+ 1 F 0.1 F 24 1 470 F + 0.1 F 2
100 F
0.1 F 5 23 VL
0.1 F
+
+5V Digital 1 F
11 VD CS/PDN CDIN/DFS 19 18 17 10 16 15
-Controller/ Configuration
VA VREF
CCLK/SM
VCOM CAL SDATA1 AINL+
+
0.1 F
Left Analog Input + 4 39 6.8nF 39 Left Analog Input Right Analog Input + 27
39
CS5396/7 A/D CONVERTER
SDATA2
Audio Data Processor
5
13 LRCK SCLK MCLKA MCLKD 20 9 14 Timing Logic & Clock
AINL-
7
AINR+ DACTL 26 AINRADCTL TSTO1 TSTO2 AGND0 LGND DGND AGND1 AGND2 3 22 12 28 25 6 8 21 TSTO pins should be left floating, with no trace attached
6.8nF
39
Right Analog Input -
Figure 1. Typical Connection Diagram
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GENERAL DESCRIPTION
The CS5396/97 is a 24-bit, stereo A/D converter designed for stereo digital audio applications. The analog input channels are simultaneously sampled by separate, patented, 7th-order tri-level delta-sigma modulators at either 128 or 64 times the output sample rate (64x Fs or 128x Fs) of the device. The resulting serial bit streams are digitally filtered, yielding pairs of 24-bit values at output sample rates (Fs) of up to 100 kHz. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converter does not require difficult-to-design or expensive anti-alias filters, and it does not require external sample-and-hold amplifiers or voltage references. Only normal power supply decoupling components, voltage reference bypass capacitors and a single resistor and capacitor on each input for antialiasing are required, as shown in Figure 1. An onchip voltage reference provides for a differential input signal range of 4.0 Vpp. The device also contains a high pass filter, implemented digitally after the decimation filter, to completely eliminate any internal offsets in the converter or any offsets present at the input circuitry to the device. Output data is available in serial form, coded as 2's complement 24-bit numbers. For more information on delta-sigma modulation techniques see the references at the end of this data sheet. * * * * * * * * 128x Oversampling Mode Reduction of 24-bit data to 20, 18 or 16-bit data with psychoacoustically optimized dither Programmability of psychoacoustic filter coefficients Peak Input Signal Level Monitor with either High Resolution or Bar Graph mode selection Signal inversion High pass filter defeat Mute Access to the digital filter to allow the input of external digital audio data to produce a two-toone decimated output and/or psychoacoustic bit reduction.
STAND-ALONE MODE Master Clock - Stand-Alone Mode
The master clock is the clock source for the deltasigma modulator sampling (MCLKA) and digital filters (MCLKD). The required MCLKA/D frequency is determined by the desired Fs and must be 256x Fs. Table 1 shows some common master clock frequencies.
LRCK (kHz) 32 44.1 48 64 88.2 96 MCLKA/D (MHz) 8.192 11.2896 12.288 16.384 22.5792 24.576 SCLK (MHz) 2.048 2.822 3.072 4.096 5.6448 6.144
Stand-Alone vs. Control Port Mode
The CS5396/97 can operate in either Stand-Alone or Control Port Mode. The functionality of pins 17, 18 and 19 is established upon entering either the Stand-Alone or Control Port mode, as described in the Pin Description section. The Control Port Mode requires a micro-controller and allows access to many additional features, which include:
Table 1. Common Clock Frequencies for Stand-Alone Mode
Serial Data Interface - Stand-Alone Mode
The CS5396/97 supports two serial data formats which are selected via the digital format select pin, DFS. The digital output format determines the relationship between the serial data, left/right clock and serial clock. Figures 2 and 3 detail the interface forDS229PP2
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CS5396 CS5397
mats. The serial data interface is accomplished via the serial data outputs; SDATA1 and SDATA2; serial data clock, SCLK, and the left/right clock, LRCK. The serial nature of the output data results in the left and right data words being read at different times. However, the samples within an LRCK cycle represent simultaneously sampled analog inputs. Internal dividers will divide MCLKA/D by 4 to generate a SCLK which is 64x Fs and by 256 to generate a LRCK which is equal to Fs. The CS5396/97 is placed in the Master mode with the slave/master pin, S/M, low.
Slave Mode - Stand-Alone Mode
LRCK and SCLK become inputs in SLAVE mode. LRCK must be externally derived from MCLKA/D and be equal to Fs. It is recommended that SCLK be equal to 64x. Other frequencies between 48x and 128x Fs are possible but may degrade system performance due to interference effects. The master clock frequency must be 256x Fs. The CS5396/97 is placed in the Slave mode with the slave/master pin, S/M, high.
Serial Data- Stand-Alone Mode
The serial data block consists of 24 bits of audio data presented in 2's-complement format with the MSB-first. The data is clocked from SDATA1 and SDATA2 by the serial clock and the channel is determined by the Left/Right clock. The full precision 24-bit data is available on SDATA1 and the output from the low group delay filter is available on SDATA2.
High Pass Filter - Stand-Alone Mode
The CS5396/97 includes a high pass filter after the decimator to remove the DC offsets introduced by the analog buffer stage and the CS5396/97 analog modulator. The characteristics of this first-order high pass filter are outlined below, for Fs equal to 48 kHz. This filter response scales linearly with sample rate. Frequency response: -3 dB @ 1.8 Hz -0.036 dB @ 20 Hz Phase deviation: 5.3 degrees @ 20 Hz Passband ripple: None
Serial Clock - Stand-Alone Mode
The serial clock shifts the digitized audio data from the internal data registers via the SDATA1 and SDATA2 pins. SCLK is an output in Master Mode where internal dividers will divide the master clock by 4 to generate a serial clock which is 64x Fs. In Slave Mode, SCLK is an input with a serial clock typically between 48x and 128x Fs. However, it is recommended that SCLK be equal to 64x, though other frequencies are possible, to avoid potential interference effects which may degrade system performance.
Power-up and Calibration - Stand-Alone Mode
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by exiting the power-down mode. However, the voltage reference will take a much longer time to reach a final value due to the presence of external capacitance on the VREF pin. A time delay of approximately 10ms/F is required after applying power to the device or after exiting a power down state.
Left/Right Clock - Stand-Alone Mode
The Left/Right clock, LRCK, determines which channel, left or right, is to be output on SDATA1 and SDATA2. In Master Mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to Fs and synchronous to MCLKA/D.
Master Mode - Stand-Alone Mode
In Master mode, SCLK and LRCK are outputs which are internally derived from the master clock.
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A calibration of the tri-level delta-sigma modulator should always be initiated following power-up and after allowing sufficient time for the voltage on the external VREF capacitor to settle. This is required to minimize noise and distortion. It is also advised that the CS5396/97 be calibrated after the device has reached thermal equilibrium, approximately 10 seconds, to maximize performance.
CONTROL PORT MODE Access to Control Port Mode
The mode selection between Stand-Alone and Control Port Mode is determined by the state of the SDATA1 pin 250 MCLK cycles following the internal power-on reset. A 47 k pull-up resistor on SDATA1 will select the Control Port Mode. However, the control port will not respond to CCLK and CDIN until the pull-up on the SDATA1 pin is released.
Synchronization of Multiple Devices Stand Alone Mode
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. It is recommended that the rising edge of the CAL signal be timed with a falling edge of MCLK to ensure that all devices will initiate a calibration and synchronization sequence on the same rising edge of MCLK. The absence of re-timing of the CAL signal can result in a sampling difference of one MCLK period.
Internal Power-On Reset
The timing required to determine Control port mode and I2S/SPI mode is based on an internal power-on reset. The internal power-on reset requires the power supply to exceed a threshold voltage. However, there is no external indication of when the internal reset is activated. If precise timing of the Control port and I2S/SPI decisions is required, MCLK should not be applied until the power supply has stabilized.
LRCK
Left
Right
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
MASTER 24-Bit Left Justified Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs
SLAVE 24-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 256x Fs
Figure 2. Serial Data Format 0, Stand-Alone Mode, DFS low. Left Justified.
LRCK Left Right
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
MASTER I2S 24-Bit Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs
SLAVE I 2S 24-Bit Data Data Valid on Rising Edge of SCLK MCLK equal to 256x Fs
Figure 3. Serial Data Format 1, Stand-Alone Mode, DFS High. I2S compatible
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Master Clock - Control Port Mode
The master clock is the clock source for the deltasigma modulator sampling (MCLKA) and digital filters (MCLKD). The required MCLKA/D frequency is determined by the desired Fs and the chosen Oversampling Mode. Table 2 shows some common master clock frequencies. clock. Figures 4 - 7 detail the interface formats. The serial data interface is accomplished via the serial data outputs; SDATA1 and SDATA2, serial data clock, SCLK, and the left/right clock, LRCK. The serial nature of the output data results in the left and right data words being read at different times. However, the samples within an LRCK cycle represent simultaneously sampled analog inputs.
64x vs. 128x Oversampling Modes
The CS5396/97 can operate in a 64x Oversampling Mode with a 256x master clock (MCLKA/D) at a maximum sample rate of 100 kHz. The device can also operate in a 128x Oversampling Mode with a 512x master clock (MCLKA/D) where the maximum Fs is 50 kHz. Notice that the required master clock is 24.576 MHz for Fs equal to either 48 kHz in the 128x Oversampling Mode or 96 kHz in the 64x Oversampling Mode. The sampling mode is set via the control register which alters the decimation ratio of the digital filter. The 64x Oversampling Mode is the default mode. Table 2 shows some common clock frequencies for both modes. Refer to Appendix A for additional discussion of 64x vs. 128x Oversampling Modes.
LRCK (kHz) 32 44.1 48 32 44.1 48 64 88.2 96 Oversampling 64 64 64 128 128 128 64 64 64 MCLKA/D (MHz) 8.192 11.2896 12.288 16.384 22.5792 24.576 16.384 22.5792 24.576 SCLK (MHz) 2.048 2.822 3.072 4.096 5.6448 6.144 4.096 5.6448 6.144
Serial Data - Control Port Mode
The serial data block is presented in 2's-complement format with the MSB-first. The data is clocked from SDATA1 and SDATA2 by the serial clock and the channel is determined by the Left/Right clock. The full precision 24 bit data is available on SDATA1 and the output from the low group delay is available on SDATA2. The serial data can be followed by 8 Peak Signal Level, PSL, bits as shown in Figures 4 - 7 if the PKEN bit is set. Refer to the Dual Audio Output section of this data sheet for further discussion of SDATA1 and SDATA2 options.
Serial Clock - Control Port Mode
The serial clock shifts the digitized audio data from the internal data registers via SDATA1 and SDATA2. SCLK is an output in Master Mode where internal dividers will divide the master clock by 4 to generate a serial clock which is 64x Fs in the 64x Oversampling Mode. In the 128x Oversampling Mode, internal dividers will divide MCLKA/D by 4 to generate a SCLK which is 128x Fs. In Slave Mode, SCLK is an input with a serial clock typically between 48x and 128x Fs. It is recommended that SCLK be equal to 64x in the 64x Oversampling Mode and equal to 128x in the 128x Oversampling Mode to avoid possible system performance degradation due to interference effects.
Table 2. Common Clock Frequencies
Serial Data Interface - Control Port Mode
The CS5396/97 supports two serial data formats which are selected via the control register. The digital output format determines the relationship between the serial data, left/right clock and serial
Left/Right Clock -Control Port Mode
The Left/Right clock, LRCK, determines which channel, left or right, is to be output on SDATA1
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LRCK
Left
Right
SCLK
SDATA
24 23
9
8
7
6
5
4
3
2
1
0 P7 P6 P5 P4 P3 P2 P1 P0 24 23
9
8
7
6
5
4
3
2
1
0 P7 P6 P5 P4 P3 P2 P1 P0 24 23
MASTER 24-Bit Left Justified Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs
SLAVE 24-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 256x Fs
Figure 4. Control Port Mode, Serial Data. Left Justified. 64x Oversampling Mode The peak signal level bits are available only if Bit 6 of Byte 7 is set.
LRCK Left Right
SCLK
SDATA
24 23
9
8
7
6
5
4
3
2
1
0 P7 P6 P5 P4 P3 P2 P1 P0 24 23
9
8
7
6
5
4
3
2
1
0 P7 P6 P5 P4 P3 P2 P1 P0 24 23
MASTER I2S 24-Bit Data Data Valid on Rising Edge of 64x SCLK MCLK equal to 256x Fs
SLAVE I 2S 24-Bit Data Data Valid on Rising Edge of SCLK MCLK equal to 256x Fs
Figure 5. Control Port Mode, Serial Data. I2S Compatible. 64x Oversampling Mode. The peak signal level bits are available only if Bit 6 of Byte 7 is set.
LRCK
Left
Right
SCLK
SDATA
23 22
1
0 P7 P6 P5 P4 P3 P2 P1 P0
23 22
1
0 P7 P6 P5 P4 P3 P2 P1 P0
23 22
MASTER 24-Bit Left Justified Data Data Valid on Rising Edge of 128x SCLK MCLK equal to 512x Fs
SLAVE 24-Bit Left Justified Data Data Valid on Rising Edge of SCLK MCLK equal to 512x Fs
Figure 6. Control Port Mode, Serial Data. Left Justified. 128x Oversampling Mode The peak signal level bits are available only if Bit 6 of Byte 7 is set.
LRCK
Left
Right
SCLK
SDATA
23 22
1
0 P7 P6 P5 P4 P3 P2 P1 P0
23 22
1
0 P7 P6 P5 P4 P3 P2 P1 P0
23 22
MASTER I2S 24-Bit Data Data Valid on Rising Edge of 128x SCLK MCLK equal to 512x Fs
SLAVE I2S 24-Bit Data Data Valid on Rising Edge of SCLK MCLK equal to 512x Fs
Figure 7. Control Port Mode, Serial Data. I2S Compatible. 128x Oversampling Mode. The peak signal level bits are available only if Bit 6 of Byte 7 is set.
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and SDATA2. In Master Mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to Fs and synchronous to MCLKA/D. devices to have individual addresses, synchronization can be accomplished by; 1) Disable the address enable bit (ADDREN) in register 7 2) Issue a system broadcast FSTART command synchronized with CCLK. 3) Reset the ADDREN bit.
Master Mode- Control Port Mode
In Master mode, SCLK and LRCK are outputs which are internally derived from the master clock. In the 64x Oversampling Mode, internal dividers will divide MCLKA/D by 4 to generate a SCLK which is 64x Fs and by 256 to generate a LRCK which is equal to Fs. In the 128x Oversampling Mode, internal dividers will divide MCLKA/D by 4 to generate a SCLK which is 128x Fs and by 512 to generate a LRCK which is equal to Fs. The CS5396/97 is placed in the Master mode via the control register.
Power-up and Calibration - Control Port Mode
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by exiting the power-down mode. However, the voltage reference will take a much longer time to reach a final value due to the presence of external capacitance on the VREF pin. A time delay of approximately 10ms/F is required after applying power to the device or after exiting a power down state. A calibration of the tri-level delta-sigma modulator should always be initiated following power-up and after allowing sufficient time for the voltage on the external VREF capacitor to settle. This is required to minimize noise and distortion. It is also advised that the CS5396/97 be calibrated after the device has reached thermal equilibrium to maximize performance. A calibration sequence requires the following commands; 1) set the FSTART bit 2) set the GND CAL bit 3) set the CAL bit 4) Wait a minimum of 2050 LRCK periods in the 128x mode or 4100 LRCK periods in the 64x mode. 5) Remove GND CAL
Slave Mode - Control Port Mode
LRCK and SCLK become inputs in SLAVE mode. LRCK must be externally derived from MCLKA/D and be equal to Fs. It is recommended that SCLK be equal to 64x in the 64x Oversampling Mode and equal to 128x in the 128x Oversampling Mode. Other frequencies are possible but may degrade system performance due to interference effects. The CS5396/97 is placed in the Slave mode via the control register.
Synchronization of Multiple Devices Control Port Mode
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. The FSTART bit in register 1 controls the synchronization of the internal clocks and sampling process between the analog modulator and the digital filter. Multiple ADCs can be synchronized if the FSTART command is initiated on the same edge of MCLK. This can be accomplished by re-timing the CCLK clock with the falling edge of MCLK. This is a relatively simple matter if the ADCs have the same address. However, if the system requires the
High Pass Filter -Control Port Mode
The CS5396/97 includes a high pass filter after the decimator to remove the DC offsets introduced by
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the analog buffer stage and the CS5396/97 analog modulator. The high pass filter can be defeated with the control register. It is also possible to write to the left/right offset registers to establish a predetermined offset. The characteristics of this first-order high pass filter are outlined below for Fs equal to 48 kHz. The filter response scales linearly with sample rate. Frequency response: -3 dB @ 1.8 Hz -0.036 dB @ 20 Hz Phase deviation: 5.3 degrees @ 20 Hz Passband ripple: None P7 - Overrange 0 - Analog input less than full-scale level 1 - Analog input greater than full-scale P6 - Idle channel 0 - Analog input >-60 dB from full-scale 1 - Analog input <-60 dB from full-scale P5 to P0 - Input Level Bits (1 dB steps) Inputs <0 dB P5 - P0 0 dB 000000 -1 dB 000001 -2 dB 000010 -60 dB 111100
Input Level Monitoring - Control Port Mode
The CS5396/97 includes independent Peak Input Level Monitoring for each channel. The analog-todigital converter continually monitors the peak digital signal for both channels and records these values in the Active registers. This information can be transferred to the Output registers by writing the PU (Peak Update) bit which will also reset the Active register. The Active register contains the peak signal level since the previous peak update request. The 8-bit contents of the output registers are available in both interface modes. The peak signal level information is available in two formats - High Resolution Mode and Bar Graph Mode. The output format is controlled via the control register.
Bar Graph Mode
This mode provides a decoded output format which indicates the peak input signal level in a "Bar Graph" format which can be used to drive front panel LEDs. This decoded output can be used to drive front panel LEDs. Input Level Overflow 0 dB to -3 dB -3 dB to -6 dB -6 dB to -10 dB -10 dB to -20 dB -20 dB to -30 dB -30 dB to -40 dB -40 dB to -60 dB < - 60 dB T7 - T0 11111111 01111111 00111111 00011111 00001111 00000111 00000011 00000001 00000000
High Resolution Mode
Bits P7-P0 indicate the Peak Signal Level (PSL) since the previous peak update (or previous write of the PU bit). If the ADC input level is less than fullscale, bits P5-P0 represent the peak value from 60 dB to 0 dB of full scale in 1 dB steps. The PSL outputs are accurate to within 0.25 dB. Bit P6 provides a coarse means of determining an ADC input idle condition. Bit P7 indicates an ADC overflow condition if the ADC input level is greater than full-scale.
Dual Digital Audio Outputs
The CS5396/97 contains two stereo digital audio output channels - SDATA1 and SDATA2. These audio output channels are completely independent, as SDATA1 can contain 24-bit audio data simultaneous with psychoacoustic audio data on SDATA2. Another example of this independence is 24-bit audio data output on SDATA1 simultaneously with a low group delay output on SDATA2. The audio output formats are completely programmable through the I2C/SPI C interface. The output
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formats include: inverted output, psychoacoustic output (16-bit, 18-bit, 20-bit), and low group delay output. that is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. The CS5396/97 has a MAP auto increment, which will increment the MAP after each byte is written, allowing block writes of successive registers.
Psychoacoustic Filter
The CS5396/97 includes a programmable 10 tap digital filter which can be used to perform psychoacoustic noise-shaping of the audio spectrum if desired. The filter can implement a variety of 16bit, 18-bit, or 20-bit noise-shaped responses by setting the digital filter coefficients. Further discussion of the psychoacoustic filter can be found in Appendix C. Appendix B discusses an application using the psychoacoustic filter independently of the A/D converter function. In this mode, SDATA2 becomes an input to the psychoacoustic filter stage and SDATA1 is the digital audio output.
I2C Mode
In I2C mode, CDIN is a bidirectional data line. Data is clocked into and out of the part by CCLK. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the Memory Address Pointer will be output. MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. Use of the I2C bus compatible interface requires a license from Philips. I2C bus in a registered trademark of Philips Semiconductors.
Low Group Delay Filter
The characteristics of the low group delay filter are shown in Figures 17 - 24.
C Interface Formats
The device supports either SPI or I2C interface formats. The CS5396/97 monitors the state of CS during power-up and will configure to an SPI interface if the pin is held low. Conversely, if the pin is held high, the port will configure to a I2C interface.
Establishing the Chip Address in I2C Mode
Connecting SDATA1 pin and CS to 5 volts during power-up will set the device to the Control Port and I2C mode. However, the control port will not respond to CCLK and CDATA until the hold on the SDATA1 pin is released. The chip address can be set by: 1) Release the hold on the SDATA1 pin of the device to be addressed. 2) Program the chip address and set the Address Enable bit, addren, which will prevent further communication to this device without the correct address. 3) Repeat steps 1 and 2 for the remaining devices on the bus.
SPI Mode
In SPI mode, CS is the chip select signal, CCLK is the C bit clock and CDIN is the input data line from the microcontroller. Notice that it is not possible to read the CS5396/97 registers in SPI mode due to the lack of a data output pin. To write to a register, bring CS low. The first 7 bits on CDIN are the chip address, and must be zero. The eighth bit is a read/write indicator (R/W) which must be low. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register
DS229PP2
ANALOG CONNECTIONS - ALL MODES
Figure 1 shows the analog input connections. The analog inputs are presented differentially to the
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CS5396 CS5397
modulators via the AINR+/- and AINL+/- pins. Each analog input will accept a maximum of 2.0 Vpp. The + and - input signals are 180 out of phase resulting in a differential input voltage of 4.0 Vpp. Figure 8 shows the input signal levels for full scale.
CS5396/97
+3.5 V +2.5 V
AIN+
+1.5 V +3.5 V +2.5 V
+1.5 V
AIN-
to the sensitivity of this node, the circuit traces attached to these pins must be minimal in length and no load current may be taken from VREF. It is possible to use VCOM as a reference voltage to bias the input buffer circuits, if the circuit trace is very short and VCOM is buffered at the converter (refer to the CDB53965/97). The recommended decoupling scheme for VREF, Figure 1, is a 470 F electrolytic capacitor and a 0.1 F ceramic capacitor connected from VREF to AGND. The recommended decoupling scheme for VCOM, Figure 1, is a 100 F electrolytic capacitor and a 0.1 F ceramic capacitor connected from VCOM to AGND.
Full Scale Input level= (AIN+) - (AIN-)= 4.0 Vpp
Figure 8. Full scale input voltage
GROUNDING AND POWER SUPPLY DECOUPLING - ALL MODES
As with any high resolution converter, the ADC requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 shows the recommended power arrangements, with VA and VL connected to a clean +5 V supply. VD, which powers the digital filter, should be run from the system +5 V logic supply, provided that it is not excessively noisy (< 50 mV pk-to-pk). Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. The printed circuit board layout should have separate analog and digital regions and ground planes, with the ADC straddling the boundary. All signals, especially clocks, should be kept away from the VREF pin in order to avoid unwanted coupling into the modulators. The VREF decoupling capacitors, particularly the 0.01 F, must be positioned to minimize the electrical path from VREF and pin 3, AGND. The CDB5396/97 evaluation board demonstrates the optimum layout and power supply arrangements, as well as allowing fast evaluation of the ADC. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
The analog modulator samples the input at 6.144 MHz (MCLK=24.576 MHz) corresponding to Fs equal to 48 kHz in the 128x Oversampling Mode and Fs equal to 96 kHz in the 64x Oversampling Mode. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,...A 39 resistor in series with the analog input and a 6.8 nF COG capacitor between the inputs will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. If active circuitry precedes the ADC, it is recommended that the above RC filter is placed between the active circuitry and the AINR and AINL pins. The above example frequencies scale linearly with output sample rate. The on-chip voltage reference and the common mode voltage are available at VREF and VCOM for the purpose of decoupling only. However, due
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DIGITAL FILTER PLOTS
Figures 9-24 show the performance of the digital filters included in the ADC. All plots are normalized to Fs. Assuming a sample rate of 48 kHz, the 0.5 frequency point on the plot refers to 24 kHz. The filter frequency response scales precisely with Fs.
Magnitude (dB)
Magnitude (dB)
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Figure 9. CS5396 Stop Band Attenuation
Figure 10. CS5396 Passband Ripple
Magnitude (dB)
Normalized Frequency (Fs)
Magnitude (dB)
Normalized Frequency (Fs)
Figure 11. CS5396 Transition Band
Figure 12. CS5396 Transition Band
DS229PP2
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CS5396 CS5397
Normalized Frequency (Fs)
Magnitude (dB)
Magnitude (dB)
Normalized Frequency (Fs)
Figure 13. CS5397 Stop Band Attenuation
Figure 14. CS5397 Passband Ripple
Magnitude (dB)
Normalized Frequency (Fs)
Magnitude (dB)
Normalized Frequency (Fs)
Figure 15. CS5397 Transition Band
Figure 16. CS5397 Transition Band
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Magnitude (dB)
Normalized Frequency (Fs)
Magnitude (dB)
Normalized Frequency (Fs)
Figure 17. Low Group Delay Filter Stop Band Attenuation 64x Oversampling Mode
Figure 18. Low Group Delay Filter Passband Ripple 64x Oversampling Mode
Normalized Frequency (Fs)
Magnitude (dB)
Magnitude (dB)
Normalized Frequency (Fs)
Figure 19. Low Group Delay Filter Transition Band 64x Oversampling Mode
Figure 20. Low Group Delay Filter Transition Band 64x Oversampling Mode
DS229PP2
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Figure 21. Low Group Delay Filter Stop Band Attenuation 128x Oversampling Mode
Figure 22. Low Group Delay Filter Passband Ripple 128x Oversampling Mode
Figure 23. Low Group Delay Filter Transition Band 128x Oversampling Mode
Figure 24. Low Group Delay Filter Transition Band 128x Oversampling Mode
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REGISTER DESCRIPTION
** "default" ==> bit status after power-up-sequence
Analog control (address 00000001)
7 fstart 0 6 gndcal 0 5 aapd 0 4 adpd 0 3 1bit 0 2 1 0
FSTART (Frame start)Default = `0'. This bit must be set to `1' to synchronize the modulator output and the decimation filter input and is automatically reset to `0' after a "fstart" pulse is sent to the analog and digital block. GNDCAL (Ground calibration enable) Default = `0'. Modulator input is tied to internal "Vcom" when this bit is `1'. AAPD (Analog Section of modulator in power down) Default = `0'. The analog section of the modulator is in power down mode when aapd = `1'. ADPD (Digital Section of modulator in power down) Default = `0'. The digital section on the modulator is in power down mode when adpd = `1'. TEST BIT Default ='0'. Must remain at 0.
Mode (address 00000010)
7
128x/64x
0
6 cal 0
5 change_sign 0
4 _LR/LL 0
3 _hpen 0
2 s/_m 0
1 DFS 0
0 mute 0
128x/64x
Default = `0'. Oversampling ratio is 128 when this bit is `1' and 64 when this bit is `0'.
CAL (System calibration enable) Default = `0'. Setting this bit to `1' will initiate calibration. This bit is automatically reset to `0' following calibration. Change_sign (Change Sign enable) Default = `0'. A `1' will interchange the analog input paths within each channel resulting in a phase inversion of the analog signal. This bit applies to both channels. _LR/LL (Left-Right output disable) Default = `0'. If this bit is `0', SDATA1 will output the Left and Right channel data from the sdata1 source and SDATA2 will output the Left and Right channel data from the sdata2 source as described elsewhere in the data sheet. If this bit is set to `1', the Left channel data from sdata1 source and sdata2 source (stored in Audio port register) will be sent out in SDATA1. SDATA2 will output all the Right channel data.
DS229PP2
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HPEN (HP enable) Default = `0'. The highpass filter will be disabled when _HPEN = `1'. The highpass filter will be automatically enabled following calibration. S/_M (Slave / Master mode) Default = `0'. In master mode, LRCK, and SCLK are outputs. In slave mode, LRCK and SCLK are inputs. This bit is ignored when sdata1 is used as input port in "fir2in" or "psychoin" mode (refer to Digital control & Tag register and Appendix B). DFS (Digital Format Select)Default = `0'. Output of serial data complies with I2S standard when DFS is 1. put of serial data is Left Justified when DFS is 0. MUTE Default = `0'. Data at SDATA1 and SDATA2 is always `0' when this set to `1'. Out-
Audio port (address 00000011)
7 24bit (sdata1) 1 6 24bit (sdata2) 0 5 psycho (sdata1) 0 4 psycho (sdata2) 0 3 psel18/_16 0 2 psel20/_16 0 1 lgd (sdata1) 0 0 lgd (sdata2) 1
24bit(SDATA1)
Default = `1'. A `1' enables the serial audio port 1 to transmit the 24-bit high precision output. This bit must be set to `0' to enable other SDATA1 output options. Default = `0'. A `1' enables the serial audio port 2 to transmit 24-bit high precision output. This bit must be set to `0' to enable other SDATA2 output options. Default = `0'. psychoacoustic output will be the data at the serial audio port 1 if this bit is `1' and all other bits of the port are set to `0'. Default = `0'. psychoacoustic output will be the data at the serial audio port 2 if this bit is `1' and all other bits of the port are set to `0'.
24bit(SDATA2)
psycho(SDATA1)
psycho(SDATA2)
psel18/_16(Psycho 18bit or 16bit) Default = `0'. This bit indicates the number of output bit if the psychoacoustic filter is chosen as output. A `0' here allows 16 bits output whereas a `1' allows 18 bits output as long as "psel20/_16" is `0'. psel20/_16(Psycho 20bit) Default = `0'. This bit has the highest priority when setting the number of output bit of psychoacoustic filter. If this bit is `1', the output is set to 20-bit regardless of the status of "psel18/_16". LGD(sdata1) Default = `0'. 24-bit low-group-delay filter output will go through a highpass filter if "_hpen" bit in the Mode register is `0'. The LGD output will be the data at the serial audio port 1 if this bit is `1' and all other bits of the port set to `0'. Default = `1'. DS229PP2
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CS5396 CS5397
24-bit low-group-delay filter output will go through a high passfilter if "_hpen" bit in the Mode register is `0'. If "_hpen" is `1', data at the serial audio port will derive directly from the LGD filter output. If more than 1 bit is set for sdata2, low-group-delay filter output will be selected for output at the port.
Test Mode 0(address 00000100)
7 aoverflow 0 6 doverflow 0 5 fir1_en 0 4 fir1(LRCK) 0 3 _psydither 0 2 dstart1 0 1 dstart0 0 0
aoverflow doverflow fir1_en(sdata)
A `1' indicates an overflow condition occurs in the modulator. This bit is reset by reading the register. A `1' indicates an overflow condition occurs in the decimation filter. This bit is reset by reading the register. Default = `0'. Test purpose only.
fir1L_R(fir1 L channel enable) Default = `0'. Test purpose only. _psydither(psychoacoustic filter dither disable) Default = `0'. A `0' means adding dither in the psychoacoustic filter. dstart1, dstart2(dstart control bits) Default = `00'. Test purpose only.
Test Mode 1(add 00000101)
7 6 5 4 3 test mode. reserved for factory use only 2 1 0
FOR FACTORY USE ONLY
Chip Address (address 00000110)
7 6 caddr6 0 5 caddr5 0 4 caddr4 0 3 caddr3 0 2 caddr2 0 1 caddr1 0 0 caddr0 0
caddr(6-0) (chip address (bit6 to bit0)) Default = `0000000'. This is used to store the programmable chip address for I2C and SPI mode. When more than 1 device are connected to the I2C or SPI buses and using chip address is necessary, chip address set up is done by: 1) Hold the SDATA1 pin of every chip to `1' during power up. DS229PP2 27
CS5396 CS5397
2) Release the SDATA1 pin of the chip that is going to be programmed with chip address. 3) Send chip address and "addren"='1' (in Register 7) through the serial control port. (The remaining devices will not repond to this request.) 4) Repeat step 2) and step 3) for to other chips one-by-one. (SDATA1 output is tri-stated until it is released from pull up.)
Digital Control & Peak Signal Level (address 00000111)
7 ADDREN 0 6 pken 0 5 pkupdate 0 4 hr/_bg 0 3 2 ddpd 0 1 fir2in 0 0 psychoin 0
addren(chip address enable) Default = `0'. When this bit is `0', no chip address comparison is done. The chip will response to all the request from Control Port. When this bit is `1', the chip responds to the C only if the chip address from the C matches the chip address stored in "caddr(6-0)".
pken(PEAK enable) Default = `0'. PSL bits calculation is based on the high precision 24-bit output. PSL bits output follows the serial audio port that sends out 24-bit data. If this bit is disabled, the PSL bits location on the output stream will be replaced by zeros. pkupdate(PEAK update) Default = `0'. A `0' to `1' transition will load the peak value (since the last update) to the appropriate serial audio port. The internal peak register will then reset to `0'. hr/_bg(PEAK display format) Default = `0'. High resolution tag format (hr/_bg='1') converts the 24-bit decimation filter output into 1 dB step. Bar Graph tag format (hr/_bg='0') allows LCD display format of the 24-bit output with 8 discrete values. ddpd(digital filter power down enable) Default = `0'. The digital filter and serial audio port is in power down mode when ddpd = `1'. fir2in(external fir2 input enable) Default = `0'. Input of 2nd stage decimation filter is taken from the sdata2 port. The input data will be decimated by 2 and then output to sdata1 of serial audio port. psychoin (external psychoacoustic filter input enable) Default = `0'. Input of psychoacoustic filter is taken from the sdata2 port. The 24-bit input data will be truncated in psychoacoustic filter to the chosen output word length and then output to sdata1 of serial audio port.
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R_cal_coeff (address 00001000 - 00001010)
7 ralpha (bit7) 0 ralpha (bit15) 0 ralpha (bit23) 0 6 ralpha (bit6) 0 ralpha (bit14) 0 ralpha (bit22) 1 5 ralpha (bit5) 0 ralpha (bit13) 0 ralpha (bit21) 0 4 ralpha (bit4) 0 ralpha (bit12) 0 ralpha (bit20) 0 3 ralpha (bit3) 0 ralpha (bit11) 0 ralpha (bit19) 0 2 ralpha (bit2) 0 ralpha (bit10) 0 ralpha (bit18) 0 1 ralpha (bit1) 0 ralpha (bit9) 0 ralpha (bit17) 0 0 ralpha (bit0) 0 ralpha (bit8) 0 ralpha (bit16) 0
Default = `0000 0000 0000 0000 0100 0000'. (represents 1) The right channel calibration factor is stored in these registers with MSB in bit 7 of register address 00001010. This value is updated after every calibration cycle. User can read from or write to this calibration factor through the serial control port.
L_cal_coeff (address 00001011 - 00001101)
7 lalpha (bit7) 0 lalpha (bit15) 0 lalpha (bit23) 0 6 lalpha (bit6) 0 lalpha (bit14) 0 lalpha (bit22) 1 5 lalpha (bit5) 0 lalpha (bit13) 0 lalpha (bit21) 0 4 lalpha (bit4) 0 lalpha (bit12) 0 lalpha (bit20) 0 3 lalpha (bit3) 0 lalpha (bit11) 0 lalpha (bit19) 0 2 lalpha (bit2) 0 lalpha (bit10) 0 lalpha (bit18) 0 1 lalpha (bit1) 0 lalpha (bit9) 0 lalpha (bit17) 0 0 lalpha (bit0) 0 lalpha (bit8) 0 lalpha (bit16) 0
Default = `0000 0000 0000 0000 0100 0000'. (represents 1) The left channel calibration factor is stored in these registers with MSB in bit 7 of register address 00001101. This value is updated after every calibration cycle. User can read from or write to this calibration factor through the serial control port.
L_offset (address 00001110)
7 los(bit13) 0 6 los(bit12) 0 5 los(bit11) 0 4 los(bit10) 0 3 los(bit9) 0 2 los(bit8) 0 1 los(bit7) 0 0 los(bit6) 0
Default = `0000 0000'. User can read or write this offset through the serial control port.
R_offset (address 00001111)
7 ros(bit13) 0 6 ros(bit12) 0 5 ros(bit11) 0 4 ros(bit10) 0 3 ros(bit9) 0 2 ros(bit8) 0 1 ros(bit7) 0 0 ros(bit6) 0
Default = `0000 0000'. User can read or write this offset through the serial control port. DS229PP2 29
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Psycho coeff (address 00010000 - 00011000)
7 pc8(bit8) 1 pc7(bit8) 0 pc6(bit8) 1 pc5(bit8) 0 pc4(bit8) 1 pc3(bit8) 0 pc2(bit8) 1 pc1(bit8) 0 pc0(bit8) 1 6 pc8(bit7) 1 pc7(bit7) 0 pc6(bit7) 1 pc5(bit7) 1 pc4(bit7) 1 pc3(bit7) 0 pc2(bit7) 1 pc1(bit7) 0 pc0(bit7) 1 5 pc0(bit5) 0 pc1(bit5) 1 pc2(bit5) 0 pc3(bit5) 0 pc4(bit5) 0 pc5(bit5) 1 pc6(bit5) 1 pc7(bit5) 0 pc8(bit5) 1 4 pc8(bit4) 1 pc7(bit4) 1 pc6(bit4) 0 pc5(bit4) 0 pc4(bit4) 0 pc3(bit4) 0 pc2(bit4) 0 pc1(bit4) 0 pc0(bit4) 1 3 pc8(bit3) 1 pc7(bit3) 0 pc6(bit3) 0 pc5(bit3) 0 pc4(bit3) 1 pc3(bit3) 0 pc2(bit3) 1 pc1(bit3) 1 pc0(bit3) 1 2 pc8(bit2) 0 pc7(bit2) 1 pc6(bit2) 0 pc5(bit2) 0 pc4(bit2) 0 pc3(bit2) 0 pc2(bit2) 1 pc1(bit2) 0 pc0(bit2) 1 1 pc8(bit1) 1 pc7(bit1) 0 pc6(bit1) 1 pc5(bit1) 1 pc4(bit1) 1 pc3(bit1) 1 pc2(bit1) 0 pc1(bit1) 0 pc0(bit1) 1 0 pc8(bit0) 0 pc7(bit0) 1 pc6(bit0) 0 pc5(bit0) 1 pc4(bit0) 1 pc3(bit0) 1 pc2(bit0) 0 pc1(bit0) 1 pc0(bit0) 1
Please see Appendix C at the end of this document
H1 Default = `1101 1010'. H2 Default = `0011 0101'. H3 Default = `1100 0010'. H4 Default = `0100 0011'. H5 Default = `1100 1011'. H6 Default = `0010 0011'. H7 Default = `1110 1100'. H? Default = `0000 1001'. H8 Default = `1111 1111'. Psychoacoustic filter coefficients. 2's complement representation. 4 MSB bits represent left of binary point. 4 LSB represent right of binary point. User can read or write one or all of the coefficients through the serial control port.
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PIN DESCRIPTIONS
Power Supply Connections
VA - Positive Analog Power, Pin 24. Positive analog supply. Nominally +5 volts. VL - Positive Logic Power, Pin 23. Positive logic supply for the analog section. Nominally +5 volts. AGND - Analog Ground, Pin 3, 25 and 28. Analog ground reference. LGND - Logic Ground, Pin 22 Ground for the logic portions of the analog section. VD - Positive Digital Power, Pin 11. Positive supply for the digital section. Nominally +5 volts. DGND - Digital Ground, Pin 12. Digital ground for the digital section.
Analog Inputs
AINR-, AINR+ - Differential Right Channel Analog Inputs, Pin 26, 27. Analog input connections for the right channel differential inputs. Nominally 4.0 Vpp differential for full-scale digital output.
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AINL-, AINL+ - Differential Left Channel Analog Inputs, Pin 4,5. Analog input connections for the left channel differential inputs. Nominally 4.0 Vpp differential for full-scale digital output.
Analog Outputs
VCOM - Common Mode Voltage Output, Pin 2. Nominally +2.5 volts. Requires a 100 F electrolytic capacitor in parallel with 0.1 F ceramic capacitor for decoupling to AGND. Caution is required if this output is to be used to bias the analog input buffer circuits. Refer to text. VREF - Voltage Reference Output, Pin 1. Nominally +4.0 volts. Requires a 470 F electrolytic capacitor in parallel with 0.1 F ceramic capacitor for decoupling to AGND.
Digital Inputs
ADCTL - Analog Control Input, Pin 6. Must be connected to DACTL. This signal enables communication between the analog and digital circuits. MCLKA - Analog Section Input Clock, Pin 7. This clock is internally divided and controls the delta-sigma modulators. The required MCLKA frequency is determined by the desired output sample rate (Fs). MCLKA of 24.576 MHz corresponds to an Fs of 96 kHz in 64x Oversampling Mode and 48 kHz in 128x Oversampling Mode. MCLKD - Digital Section Input Clock, Pin 20. MCLKD clocks the digital filter and must be connected to MCLKA. The required MCLKD frequency is determined by the desired output sample rate (Fs). MCLKD of 24.576 MHz corresponds to an Fs of 96 kHz in 64x Oversampling Mode and 48 kHz in 128x Oversampling Mode.
Digital Input Pin Definitions for Stand-Alone MODE
DFS - Digital Format Select, Pin 18. The relationship between LRCK, SCLK and SDATA is controlled by the DFS pin. When high, the serial output data format is I2S compatible. The serial data format is left-justified when low. PDN - Power-Down, Pin 19. When high, the device enters power-down. Upon returning low, the device enters normal operation. Calibration of the device is required following release of power-down.
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S/M - Slave or Master Mode, Pin 17. When high, the device is configured for Slave mode where LRCK and SCLK are inputs. The device is configured for Master mode where LRCK and SCLK are outputs when S/M is low. CAL - Calibration, Pin 10. Activates the calibration of the tri-level delta-sigma modulator.
Digital Pin Definitions for CONTROL-PORT MODE
CDIN - Control Port Data Input, Pin 18. Control port data input for SPI mode. Control port data input and output for I2C mode. CS - Chip Select Input, Pin 19. Control port chip select for SPI mode. The CS5396/97 monitors the state of CS during powerup and will configure to an SPI interface if this pin is held low. Conversely, if held high, the port will configure to a I2C interface. CCLK - Control Port Clock Input, Pin 17. Control port clock input pin for both I2C and SPI modes. CAL - Calibration, Pin 10. CAL pin is not functional in Control Port Mode and should be connected to ground.
Digital Outputs
DACTL- Digital to Analog Control Output, Pin 9. Must be connected to ADCTL. This signal enables communication from the digital circuits to the analog circuits. SDATA1 - Digital Audio Data Output #1, Pin 16. Stand-Alone Mode - The 24-bit audio data is presented MSB first, in 2's complement format. Control Port Mode - The 24 audio data bits are presented MSB first, in 2's complement format. The audio data can be followed by 8 Peak Signal Level bits which indicate the peak signal level. The additional audio data options include; 16, 18, or 20-bit data with or without psychoacoustically optimized dither; or the output of the Low Group Delay filter. The SDATA1 output is completely independent from SDATA2. The mode selection between Stand-Alone and Control Port mode is determined by the state of the SDATA1 pin during power-up. A 47 k pull-up resistor on SDATA1 will select the Control Port mode. However, the control port will not response to CCLK and CDIN until the pull-up on the SDATA1 pin is released.
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SDATA2 - Digital Audio Data Output #2, Pin 15. Stand-Alone Mode - The 24-bit low group delay audio data is presented MSB first, in 2's complement format. Control Port Mode - The 24-bit low group delay audio data is presented MSB first, in 2's complement format. The audio data can be followed by 8 peak detect bits which indicate the peak signal level. The additional audio data options include; the standard 24-bit word; 16, 18, or 20-bit data with or without psychoacoustically optimized dither. The SDATA2 output is completely independent from SDATA1.
Digital Inputs or Outputs
LRCK - Left/Right Clock, Pin 13. LRCK determines which channel, left or right, is to be output on SDATA1 and SDATA2. In master mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is an input whose frequency must be equal to Fs. Although the outputs for each channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. Stand-Alone Mode - The relationship between LRCK, SCLK and SDATA is controlled by the Digital Format Select (DFS) pin. Control Port Mode - The relationship between LRCK, SCLK and SDATA is controlled by the control register. SCLK - Serial Data Clock, Pin 14. Stand-Alone Mode- Clocks the individual bits of the serial data from SDATA1 and SDATA2. In master mode, SCLK is an output clock at 64x Fs. In slave mode, SCLK is an input which requires a continuously supplied clock at any frequency from 48x to 128x Fs (64x is recommended). The relationship between LRCK, SCLK and SDATA is controlled by the Digital Format Select (DFS) pin. Control Port Mode - Clocks the individual bits of the serial data from SDATA1 and SDATA2. In master mode, SCLK is an output clock at 128x the output sample rate in the 128x Oversampling Mode and 64x the output sample rate in the 64x Oversampling Mode. In slave mode, SCLK is an input, which requires a continuously supplied clock at any frequency from 32x to 128x the output sample rate. A 128x SCLK is preferred in the 128x Oversampling Mode and 64x SCLK is preferred in the 64x Oversampling Mode. The relationship between LRCK, SCLK and SDATA is controlled by the control register.
Miscellaneous
TSTO1, TSTO2 - Test Outputs, Pins 8 and 21. These pins are intended for factory test outputs. They must not be connected to any external component or any length of circuit trace.
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PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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ADDITIONAL INFORMATION
1) "Techniques to Measure and Maximize the Performance of a 120 dB, 24-bit, 96 kHz A/D Integrated Circuit" by Steven Harris, Steven Green and Ka Leung. Paper presented at the 103rd Convention of the Audio Engineering Society, September 1997. 2) "A 120 dB Dynamic Range, 96 kHz, 24-bit Analog-to-Digital Converter" by Kafai Leung, Sarah Zhu, Ka Leung and Eric Swanson. Paper presented at the 102nd Convention of the Audio Engineering Society, March 1997. 3) A 5 V, 118 dB Delta Sigma Analog-to-Digital Converter for Wideband Digital Audio by Ka Y. Leung, Eric J. Swanson, Kafai Leung, Sarah S. Zhu. Presented at ISSCC February, 1997, paper FP 13.6 4) "How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters" by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 5) "The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADCs" by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6) "A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range" by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 7) "An 18-Bit Dual-Channel Oversampling DeltaSigma A/D Converter, with 19-Bit Mono Application Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 8) "A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio" by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988.
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PACKAGE DIMENSIONS
A
DIM A B C D E F G H I J K L M MILLIMETERS MIN MAX 18.03 17.53 1.27 BSC 7 NOM 0.127 0.330 2.41 2.67 45 NOM 7 NOM 0.203 0.381 2 8 7.42 7.59 8.76 9.02 10.16 10.67 0.33 0.51 INCHES MIN MAX 0.690 0.710 0.050 BSC 7 NOM 0.005 0.013 0.095 0.105 45 NOM 7 NOM 0.008 0.015 8 2 0.292 0.298 0.345 0.355 0.400 0.420 0.013 0.020
28 pin SOIC
B C
D
M F E H J K L G I
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APPENDIX C: PSYCHOACOUSTIC FILTER
The psychoacoustic filter in the CS5396 is based on the paper: "Robert A. Wannamaker, Psychoacoustically Optimal Noise Shaping, Journal of the Audio Engineering Society, Vol 40, No 7/8, 1992 July/August." The default coefficients in the CS5396 are the FIR 9-tap filter coefficients described in Table 3 of the paper. Since the effective noise shaping function is (1-H), the CS5396 registers save the (1-H) function coefficients. Therefore, the negative of each filter coefficient is stored in the registers. Each coefficient is represented as a binary 2's complement number where the 4 MSB's represent the whole number of the coefficient and the 4 LSB's represent the fractional portion truncated to 4 binary bits. Default Coefficients as listed in "Robert A. Wannamaker, Psychoacoustically Optimal Noise Shaping" a1 = 2.412 a2 = -3.370 a3 = 3.937 a4 = -4.174 a5 = 3.353 a6 = -2.205 a7 = 1.281 a8 = -0.569 a9 = 0.0847 Coefficient conversion example 1: a1 = 2.412 a1 = (0010.0110) binary repesentation with the fractional portion truncated to 4 bits. -a1 = -(0010.0110) binary representation -a1 = 1101.1010 in two's complement this value is stored in register 10h. Coefficient conversion example 2: a2 = -3.370 -a2 = 3.370 -a2 = 0011.0101 binary repesentation with the fractional portion truncated to 4 bits.
-a2 = 0011.0101 in 2's complement this value is stored in register 11h.
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PSYCHO-ACOUSTIC FILTER COEFFICIENTS
7 6 5 4 3 2 1 0
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Access:
R/W in I2C and write only in SPI
Filter coefficient a1 (address 10h) Filter coefficient a2 (address 11h) Filter coefficient a3 (address 12h) Filter coefficient a4 (address 13h) Filter coefficient a5 (address 14h) Filter coefficient a6 (address 15h) Filter coefficient a7 (address 16h) Filter coefficient a8 (address 17h) Filter coefficient a9 (address 18h) Default:
a1 - 1101 1010 a2 - 0011 0101 a3 - 1100 0010 a4 - 0100 0011 a5 - 1100 1011 a6 - 0010 0011 a7 - 1110 1100 a8 - 0000 1001 a9 - 1111 1111
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